The present invention relates to memory devices and, more particularly, to a MCP (multi-chip package) memory device with a NAND flash memory on one die and a SDRAM (synchronous dynamic random access memory) together with a controller for the NAND flash memory on another die.
FIG. 1 is a partial high level block diagram of a generic prior art embedded device 10. Device 10 includes a central processing unit (CPU) 12 and three memory devices 14, 16 and 18. Memory device 14 includes a nonvolatile memory such as a NOR flash memory for storing the operating system and the pre-stored applications of device 10. Memory device 16 includes a nonvolatile memory such as a NAND flash memory accessed via a NAND controller 17, for storing the user's data and downloaded applications. Memory device 18 is a volatile memory Such as a SDRAM for run-time execution. CPU 12 communicates with memory devices 14 and 16 via a bus 20 and with memory device 18 via a bus 22.
The communication protocols of NOR flash memories, NAND flash memories and SDRAM are different. This is why device 10 needs NAND controller 17 and two different buses 20 and 22. If not for prior art technology described below, an implementation of device 10 that used NAND flash memory in memory device 16 would need three buses.
Typical signals for communicating on bus 20 with a synchronous/asynchronous external memory such as a NOR flash memory or a static random access memory (SRAM) include the following:
A[0:x]—Address
D[0:x]—Data
CE#—Chip Select
OE#—Output Enable
WE#—Write Enable
BUSY#—indicates the status of the memory device
Reset#—Reset Signal
CLK—system clock
Typical signals for communicating with SDRAM 18 on bus 22 include the following:
CLK—System Clock
CS—Chip Select
CKE—Clock Enable
BA[0:x]—Bank Address
DMQ[0:x]—Data Input/Output
A[0:x]—Row Address, Column Address
DQ[0:x]—Data Input/Output
RAS—Row Address Strobe
CAS—Column Address Strobe
WE—Write Enable
A NAND flash memory intrinsically requires a multiplexed interface for Address and Data and control signals which are not included in the signals defined for buses 20 and 22. If a NAND flash memory device were to have its own bus, the associated signals would include:
I/O [0:x]—The I/O pins are used to input command, address and data, and to output data during read operations.
CLE—controls the activating path for commands sent to the command register.
ALE—controls the activating path for address to the internal address registers.
CS—Chip Select (or, equivalently, CE—Chip Enable)
RE—serial data-out control. When active, drives the data onto the I/O bus.
WE—controls writes to the I/O port
R/B—indicates device status
In a NOR flash device, reading is random access and fast, similar to RAM (tens of nanoseconds). Writing also is random access but is slow (a few microseconds). Erasing must be done in large chunks called “blocks” and is very slow (a few hundred milliseconds).
In a NAND flash device, reading is serial rather than random access and is somewhat slow (typically 10 to 15 microseconds). Writing must be done in medium-size chunks called “pages” and is slow (a few hundred microseconds). As in the case of a NOR flash device, erasing must be done in blocks, but is much faster (a few milliseconds) than in a NOR flash device.
Recently, NAND flash memory has become an attractive option for data storage in embedded devices such as device 10. This is because of NAND flash's smaller size, lower cost and faster write speed relative to NOR flash. One of the factors that inhibits the migration from NOR flash to NAND flash in embedded devices is the non-standard interface of NAND flash. To overcome this and other limitations of NAND flash, M-Systems Flash Disk Pioneers, Ltd. of Kfar Saba, Israel introduced technology that enables a NAND flash memory device to use the same memory interface as a NOR flash memory device. This technology is implemented in FIG. 1 by NAND flash controller 17. This technology is described in the DiskOnChip® Millennium Plus Data Sheet, which is available on request from M-Systems Flash Disk Pioneers, Ltd., and which is incorporated by reference for all purposes as if fully set forth herein.
FIG. 2 is a simplified block diagram of a prior art NAND flash memory device 30, specifically M-Systems' DiskOnChip® Millennium Plus. Device 30 includes a NAND flash memory 34 and a controller 32 of NAND flash memory 34, both fabricated on a common die 36. The functional blocks of controller 32 include:
A system interface 38 for interfacing with the rest of a host system such as device 10
A configuration interface 58 for configuring device 30 to operate in 8 bit vs. 16 bit mode, cascaded configuration and hardware write protection
A protection and security-enabling block 52 including Write/Read protection and One-Time Programming (OTP), for advanced data/code security and protection
A programmable boot block 40 with execute-in-place (XIP) capability, enhanced with a download engine 42, for host system initialization capability
An error detection and error correction code block 54 for on-the-fly error handling
A data pipeline 44 through which data flows from the host system to NAND flash memory 34
A control and status block 50 that contains registers responsible for transferring the address, data and control information between the software driver and the NAND flash memory 34
A flash interface 56
A bus control block 48 for translating the host system bus address, data and control signals into valid NAND flash signals
An address decoder 46 to enable the relevant unit inside controller 32, according to the address range received from system interface 38.
More details of these functional blocks are given in the DiskOnChip® Millennium Plus Data Sheet. To the left of device 30 in FIG. 2 are shown some of the signals that device 30 exchanges with the host system.
Unlike NOR flash, in which reading is random access, NAND flash does not support execution-in-place, such as is needed to boot the host system. The inclusion of boot block 40 in controller 32 gives device 30 a boot capability that would otherwise be available only in a device such as a NOR flash memory device. Hence, device 30 or a similar device can provide the functionality of both memory device 14 and memory device 16 in device 10. Such a device 30 could be conveniently packaged inside a common MCP package with SDRAM 18. Because of the need to use two buses 20 and 22, however, such an MCP would have to have a correspondingly large number of pins.
There is thus a widely recognized need for, and it would be highly advantageous to have, a memory device including both a NAND flash memory and a SDRAM that can communicate with a host system via a single external bus.